In a semiconductor integrated circuit, a technique is generally used which suppresses operations of unused circuits by clock gating, chip enable control over a RAM (Random Access Memory) macro, or the like so as to reduce the power consumption for low power consumption. For example, the clock of a specific circuit block is controlled such that when the circuit block is not used, the supply of clock and power is blocked, whereas when the circuit block is used, the supply of clock and power is performed to thereby reduce the power consumption.
However, when the low power consumption is achieved by these techniques, the difference between the maximum power and the minimum power to be consumed by the semiconductor integrated circuit increases to also increase the difference between the maximum current and the minimum current flowing through the circuit. This leads to an increase in power supply noise to cause malfunction of the circuit or interference with positive introduction of the low power consumption technique in the semiconductor integrated circuit. Further, when an instruction of performing a plurality of arithmetic operations by one instruction such as an SIMD (Single Instruction Multiple Data) instruction is executed, a rapid current fluctuation occurs because circuit resources such as a plurality of arithmetic circuits, RAM macro, register file and so on are simultaneously operated. In a power supply system composed of a die, package, and board, when a current fluctuation occurs in a frequency band with high impedance, the power supply noise increases. For measures to suppress the power supply noise, a decoupling capacitor is mounted on the die, package, or board so that even when the current fluctuation occurs, the power noise takes an allowable value or less.
FIG. 12 is a diagram illustrating a pipeline operation in a conventional processor and examples of a current waveform and a power supply voltage waveform during the operation. In FIG. 12, a four-stage pipeline operation of an instruction fetch stage F, an instruction decode stage D, an arithmetic operation execution stage E, and a register write stage W is illustrated as an example. When instructions I11, I12, I15, I16 with small power consumption such as a logical arithmetic operation and instructions I13, I14 with large power consumption such as a floating point arithmetic operation and an SIMD instruction are executed in a mixed manner, the current increases in a period when the arithmetic operation with large power consumption is executed. Therefore, the power supply noises are generated as illustrated in the power supply voltage waveform in FIG. 12 so that the power supply voltage exceeds an allowable upper limit VH and an allowable lower limit VL in some cases. In this case, the decoupling capacitor is mounted inside a processor, on a package or the like in the conventional processor to suppress the power supply noise.
The large current fluctuation may occur in the following case. For example, when a transistor with low threshold voltage and large leak current though high speed is used in an arithmetic circuit for high-speed performance in a processor, the following control is possibly performed in order to reduce the power consumption. Power gating is performed only on the arithmetic circuit so as to suppress the leak current in a period when the arithmetic circuit is not used, or clock gating is performed on a register on a path for supplying data to the arithmetic circuit or data gating is performed on a data path to prevent waste operations of the arithmetic circuit so as to suppress the dynamic power in a period when the arithmetic circuit is not used. In these cases, if the setting operation and the release operation of the power gating, clock gating and the data gating are rapid, a rapid current fluctuation occurs to damage the power integrity (power supply quality), possibly causing malfunction of the circuit.
A technique is proposed which generates current using a circuit controlling a circuit current other than a circuit used for actual data processing and data storage to suppress the current fluctuation at switching power (for example, see Patent Document 1). Further, an instruction conversion technique such as a compiler or the like that analyzes an instruction program using a table storing information relating to whether or not circuit resources operate depending on kinds of instructions and inserts a power control instruction based on an analysis result, and a technique of determining an instruction to be executed by the processor and limiting current supply to a circuit block that is not used at execution of the instruction are proposed (see, for example, Patent Documents 2 to 4).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2005-235203
[Patent Document 2] Japanese Laid-open Patent Publication No. 2004-318502
[Patent Document 3] Japanese Laid-open Patent Publication No. 2003-296123
[Patent Document 4] Japanese Laid-open Patent Publication No. 01-155459
As described above, the power supply noise due to current fluctuation is suppressed by mounting the decoupling capacitor on the die, package, or board in the conventional semiconductor integrated circuit. However, when advancement of miniaturization in technology promotes low voltage and large current in the future to increase the current fluctuation amount per unit time in the semiconductor integrated circuit, the capacity of the capacitor for suppressing the power supply noise also increases in the above-described conventional countermeasure. The increase in capacity of the capacitor leads to an increase in die size and an increase in the number of capacitor parts mounted on the package or board, causing an increase in cost.